1. Field of the Invention
The present invention relates to a semiconductor device, which enables fabrication of the device having improved resistance characteristics by decreasing dishing of solid phase epitaxy (SPE) silicon during planarization in a landing plug forming process utilizing SPE silicon, and a method of manufacturing the same.
2. Description of the Related Art
Generally, landing plugs are polysilicon layers formed between word lines, have respective independent characteristic regions, and are connected with bit line contacts and storage node contacts connected with capacitors.
In order to form such a landing plug, a plurality of gates is formed on a semiconductor substrate, and an interlayer dielectric film is deposited thereon, such that a plurality of gates is embedded. Then, the interlayer dielectric film is selectively etched to open a landing plug-forming region, and polysilicon for a landing plug is deposited such that the thus-opened landing plug-forming region in the interlayer dielectric film is embedded.
Next, polysilicon for a landing plug is planarized to a point at which the upper parts of the gates are exposed, and thus is isolated between the gates, thereby forming a landing plug, made of polysilicon for a landing plug, between gates. Herein, planarization is carried out via use of a chemical mechanical polishing process.
In this connection, at present, in forming the landing plug in a 0.08 μm-sized semiconductor device, use of polysilicon for a landing plug, as a landing plug-forming material, leads to deterioration of interface resistance in cell regions (cell SNC N-/Rc), due to different crystal forms between the substrate and polysilicon for a landing plug, that is, because the substrate, composed of silicon (Si), is composed of single crystals, while the landing plug, composed of polysilicon (Poly Si) for a landing plug, is composed of polycrystals. As such, in order to improve interface resistance in cell regions, the landing plug has been formed utilizing solid phase epitaxy (SPE) silicon composed of single crystals like a substrate, instead of polysilicon for a landing plug.
However, formation of the landing plug via use of SPE silicon exhibits improvement in interface resistance of cell regions, but a higher degree of dishing during planarization, as compared to the use of polysilicon for a landing plug, thereby creating problems such as decreased critical dimension (CD) values of the landing plug and bit line contact.
Hereinafter, such problems will be described in more detail with reference to FIGS. 1 through 3.
FIG. 1 is a TEM showing results of comparison between formation of a landing plug using polysilicon for a landing plug and formation of a landing plug using SPE silicon. Upon referring to FIG. 1, in forming landing plug 20 between gates 10 by planarizing a landing plug-forming material, planarization via use of polysilicon for a landing plug as the landing plug-forming material exhibited dishing of 292 Å, while planarization via use of SPE silicon as the landing plug-forming material exhibited dishing of 364 Å, thus confirming that SPE silicon exhibits greater dishing than polysilicon for a landing plug.
In addition, FIG. 2 is AFM data comparing a degree of dishing between polysilicon for a landing plug and SPE silicon, after planarization for formation of a landing plug. The AFM data shows the results of dishing determined at 7 points, and it can be seen from such results that the degree of dishing occurred in formation of a landing plug using SPE silicon is greater than formation of a landing plug using polysilicon for a landing plug and 1−σ values are also greater in SPE silicon than polysilicon. As described above, when dishing during planarization for formation of a landing plug is increased, CD of a landing plug and bit line contact thereon after formation of a landing plug is decreased.
FIG. 3 is a graph showing the critical dimension (CD) of a bit line contact after etching for formation of a bit line contact on the landing plug, following formation of the landing plug, as described above, and shows results of comparison between use of polysilicon for a landing plug and SPE silicon as a landing plug-forming material. Upon reviewing the graph of FIG. 3, it can be seen that CD of a subsequent bit line contact becomes smaller, as dishing occurred in formation of a landing plug via use of SPE silicon is deeper than formation of a landing plug via use of polysilicon for a landing plug. Formation of such a small CD value leads to an increase in contact resistance.